1. Field of the Invention
The present invention relates to a flip-flop of a CMOS type semiconductor integrated circuit, in particular to a flip-flop of a master-slave type for holding logic values in a logical circuit.
2. Description of the Prior Art
The conventional flip-flop of a CMOS structure master-slave type shown in FIG. 1 has a first transfer gate TG1 positioned between a data input terminal D and a first CMOS inverter IV1, in which flip-flop an output from the first CMOS inverter IV1 is connected to an input of itself through a second inverter IV2 and a second transfer gate TG2, as well as to a third inverter IV3 through a third transfer gate TG3. An output of the third inverter IV3 is connected to its input through a fourth inverter IV4 and a fourth transfer gate TG4, as well as to a data output terminal Q.
These four transfer gates, of the first to the fourth, respectively consists of a pair of N-channel and P-channel transistors MN31 and MP31, MN34 and MP34, MN35 and MP35 and MN38 and MP38. These four inverters of the first to the fourth, respectively consists of a pair of N-channel and P-channel transistors MN32 and MP32, MN33 and MP33, MN36 and MP36, and MN37 and MP37. Here, MNXX means an N channel MOS transistor and MPXX shows a P channel MOS transistor.
In general, such a CMOS structure semiconductor integrated circuit uses a circuitry structure in which a P channel MOS transistors and N channel MOS transistors are complementarily connected similar to the transfer gates TG1 to TG4 and the inverters IV1 to IV4 above. According to such circuitry structure, when input signals from these inverters have a GND potential or a VDD potential, output signals from these inverters become a VDD potential or a GND potential and the current from VDD to GND is zero. In other words, even when multi-stage of inverters are connected in series, a constant current becomes zero.
In a low current consuming type semiconductor integrated circuit, it is general to use a CMOS logical circuit in which P channel MOS transistors and N channel MOS transistors are complementarily connected. A circuit of a master-slave type flip-flop shown in FIG. 5 has been generally used.
In FIG. 1, signals .phi.1, .phi.1, .phi.2, .phi.2 to be sent to the transfer gates TG1 to TG4 are clock signals, and .phi.1 and .phi.2 of clock signals are complementary clock signals which are not overlapped relative to each other as shown in FIGS. 2a and 2d. Signal 1 is a negative of signal .phi.1 and signal .phi.2 is a negative of signal .phi.2. The data input signal is impressed on the inverter IV1 through the transfer gate TG1 when signal .phi.1 is at its high level as shown in FIG. 2a, taken in a master flip-flop (consisting of the inverters IV1 and IV2) by the trailing edge of signal .phi.1, and is separated from the input terminal D, being held. This held data signal is outputted from the data output terminal Q at a rising edge of .phi.2 immediately after the trailing edge of signal .phi.1 through the third inverter IV3, as well as held in the slave flip-flop (consisting of the inverters IV3 and IV4).
According to the master-slave type flip-flop of the conventional CMOS structure mentioned-above, when the potential of the data output terminal Q is translated from the VDD potential to GND and signal .phi.2 becomes a VDD potential, a current flows from the VDD terminal of the first inverter IV1 to the input of the third inverter IV3 through two P channel MOS transistors MP32 of the first inverter IV1 and MP35 of the third transfer gate, so that gate terminals of both transistors MP36 and MN36 of the third inverter IV3 are charged.
When the gate terminals of MP36 and MN36 are charged and their potentials are translated from the GND potential to VDD one, a current flows from the output terminal Q to the GND terminal of the third inverter IV3 through the N channel MOS transistor of MN36, whereby the potential of the output terminal Q is translated from the VDD potential to GND one. Additionally, when the clock signal .phi.2 becomes VDD, an electric charge at the gate terminals of transistors MP36 and MN36 of the third inverter IV3 moves and a current flows to the GND terminal of the first inverter IV1 through two N channel MOS transistors and MN35 and MN32, so that the potential at the gate terminals of MP36 and MN36 is translated from the VDD potential to GND. As a result, a current flows from the VDD source to the output terminal Q via MP36 and the potential at the output terminal Q is translated from GND potential to VDD.
Potential translation time length of the output terminal Q between GND potential and VDD one is determined according to easiness of respective currents to flow. Carriers of the N channel and the P channel transistors are an electron and a positive hole, respectively. Therefore, current it is more difficult for current to flow through a P channel MOS transistor than a N channel MOS transistor and the former transistor has a longer rising time. In particular, in case there are a plurality of P channel MOS transistors in a route of current flowing from the VDD terminal, the rising time lengthens very much.
In the flip-flop shown in FIG. 1, there are two P channel MOS transistors MP32 and MP35 in a current route from the VDD terminal to the gate terminals of the transistors MP36 and MN36 of the third inverter IV3, so that the rising time of the gate terminals of MP36 and MN36 is very long. Consequently trailing time of the output terminal Q lengthens disadvantageously very much.